Digital VLSI Design Intern
Insights
-
Date posted
July 15, 2025
-
Closing date
August 14, 2025
-
Location
Delhi NCR
-
Offered Stipend
Max: ₹10,000/month
-
Duration
2 Months
-
Degree
B.Tech
-
Year of Study
Third Year
Description
bout the Role:
Work on designing digital building blocks like adders, multiplexers, and ALUs using Verilog and RTL design flows.
Responsibilities:
Design and simulate digital circuits in Verilog
Synthesize and optimize logic blocks
Collaborate with senior engineers on IP development
Ideal Candidate:
Solid grasp of digital logic and timing analysis
Proficient with ModelSim, Vivado, or similar tools
Greatness Starts Here
27 days left to apply
