ASIC Verification Intern
Insights
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Date posted
July 15, 2025
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Closing date
September 6, 2025
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Location
Delhi NCR
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Offered Stipend
Max: ₹6,000/month
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Duration
2 Months
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Degree
B.Tech
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Year of Study
Third Year
Description
About the Role:
Support ASIC verification team in writing testbenches and performing simulations.
Responsibilities:
Develop SystemVerilog testbenches
Execute simulation test cases
Analyze waveform outputs and debug
Ideal Candidate:
Good understanding of FSMs, assertions, and UVM basics
Detail-oriented with debugging skills
Greatness Starts Here
50 days left to apply
